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19-1349; Rev 1a; 10/98
ANUAL N KIT M LUATIO ATA SHEET EVA WS D FOLLO
1-Cell, Step-Up Two-Way Pager System IC
____________________________Features
o 80mA Output from 1 Cell at 90% Efficiency o 13A Idle ModeTM (coast) Current o Selectable Low-Noise PWM or Low-Current Operation o PWM Operating Frequency Synchronized to Seven Times an External Clock Source o Operates at 270kHz with No External Clock o Automatic Backup-Battery Switchover
________________General Description
The MAX847 is a complete power-supply and monitoring system for two-way pagers or other low-power digital communications devices. It requires few external components. Included on-chip are: * A 1-cell input, 80mA output, synchronous-rectified boost DC-DC regulator with a digitally controlled +1.8V to +4.9V output * Three low-noise linear-regulator outputs * Three DAC-controlled comparators for softwaredriven 3-channel A/D conversion * SPITM-compatible serial interface * Reset and low-battery (LBO) warning outputs * Charger for NiCd, NiMH, lithium battery, or storage capacitor for RF PA power or system backup * Two 1.8 (typical) serial-controlled open-drain MOSFET switches An evaluation kit for the MAX847 (MAX847EVKIT) is available to aid in design and prototyping.
Pin Configuration appears at end of data sheet.
MAX847
Ordering Information
PART MAX847EEI TEMP. RANGE -40C to +85C PIN-PACKAGE 28 QSOP
________________________Applications
Two-Way Pagers GPS Receivers 1-Cell Powered Hand-Held Equipment
____________________________________________________Typical Operating Circuit
INPUT SINGLE AA ALKALINE BATTERY 0.8V TO 1.8V LOW-BATTERY IN/OUT RESET IN/OUT SERIAL I/O LBI LBO RSIN RSO CS SCL SDI SDO DR1 DR2 DR2IN DRGND
BATT LX1 OUT PGND REG2IN
MAX847
OFS OUTPUT 2 2.85V ANALOG OUTPUT 1 3V LOGIC OUTPUT 3 1V RECEIVER TO RF PA NiCd BATTERY STACK OR STORAGE CAPACITOR
1.8 DRIVERS
REG2 REG1
RUN
COAST A/D INPUT OPTIONAL
RUN CH0 SYNC FILT REF REG3 AGND NICD
Idle Mode is a trademark of Maxim Integrated Products. SPI is a trademark of Motorola, Inc.
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769.
1-Cell, Step-Up Two-Way Pager System IC MAX847
ABSOLUTE MAXIMUM RATINGS
BATT, OUT, NICD, LBO, RSO to AGND...................-0.3V to +6V REG1, OFS, REG2, REF, R2IN to AGND ...-0.3V to (OUT + 0.3V) SCL, SDO, SDI, CS , SYNC, FILT, DR2IN, CH0, LBI, RSIN, RUN to AGND ...................-0.3V to (REG1 + 0.3V) REG3 .......................................................-0.3V to (REG2 + 0.3V) DR1, DR2 to DRGND ...............................-0.3V to (BATT + 0.3V) PGND, DRGND to AGND ......................................-0.3V to +0.3V LX1 to PGND .............................................-0.3V to (OUT + 0.3V) Continuous Power Dissipation (TA = +70C) 28-Pin QSOP (derate 8mW/C above +70C) .............640mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +165C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(OUT = 3.0V, BATT = 1.2V, NICD = 3.6V, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER GENERAL PERFORMANCE BATT Typical Operating Range (Note 2) BATT Minimum Start-Up Voltage (Note 3) Coast Mode Supply Current (Note 4) Run Mode Supply Current (Note 4) BATT Supply Current (Note 5) NICD Input Current, Standby (Note 6) NICD Input Supply Current, Backup (Note 7) NICD Input Current, Power Fail (Note 8) REG2 Supply Current (Note 4) REG3 Supply Current (Note 4) CH DAC Supply Current (Note 4) Reference Voltage DR1, DR2 On-Resistance DR1, DR2 Leakage Current SDO Output Low SDO Output High Logic Input Level Low Logic Input Level High Logic Input Current Run or Coast Mode TA = +25C REG2, REG3 and CH DAC off, VOUT = 2.8V REG2, REG3 and CH DAC on Coast mode Charger and Backup Modes off, NICD = 3.6V Backup mode, NICD = 3.6V, OUT = 3V Charger and Backup Modes off, BATT = 0V and OUT = 0V Incremental supply current when on Incremental supply current when on Incremental supply current when on IREF = 0 to 20A, OUT = 1.8V to 4.9V TA = +25C IDR = 120mA TA = -40C to +85C VDR = 5V ISDO = 100A ISDO = -100A, from REG1 Includes CS, SDI, SCL, DR2IN, SYNC, and RUN Includes CS, SDI, SCL, DR2IN, SYNC, and RUN Logic Input = 0 to 3.3V; includes CS, SDI, SCL, DR2IN, SYNC, and RUN -1 VREG1 - 0.2 0.4 VREG1 - 0.4 1 -1.5% 0.8 0.9 13 875 0.5 1.2 20 1.2 50 20 30 1.28 1.8 1 1.5% 2.8 3.6 250 200 OUT x 0.8 1.1 25 1350 2 3 40 3 V V A A A A A A A A A V nA mV V V V A CONDITIONS MIN TYP MAX UNITS
SERIAL-INTERFACE TIMING SPECIFICATIONS (Note 9) SCL Maximum Clock Rate 50% duty cycle SDI Setup Time, tDS SDI Hold Time, tDH 2
5 100 50
MHz ns ns
_______________________________________________________________________________________
1-Cell, Step-Up Two-Way Pager System IC
ELECTRICAL CHARACTERISTICS (continued)
(OUT = 3.0V, BATT = 1.2V, NICD = 3.6V, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER SCL to SDO Output Valid, tDO CS to SDO Output Valid, tDV CS to SDO Disable, tTR CS to SCL Setup Time, tCSS CS to SCL Hold Time, tCSH CS Pulse Width High, tCSW SCL Pulse Width High or Low, tCH, tCL DC-DC CONVERTER Output Current, Run Mode (Note 10) Output Current, Coast Mode (Note 10) OUT Error, Coast Mode (Note 11) OUT Error, Run Mode (Note 12) OUT DAC Step Size (Note 13) OUT Load Regulation OUT Line Regulation Maximum LX1 Duty Cycle OUT Voltage Ripple LX1 Switch Current Limit LX1 On-Resistance PHASE-LOCKED LOOP (PLL) Frequency, Free-Run Frequency, Locked Jitter (Note 14) Capture Time (Note 14) NICD CHARGER Current High Current Low OUT Error, Backup Regulator Backup-Regulator On-Resistance (Note 15) TA = +25C, FILT connected to REF fSYNC = 38.4kHz fSYNC = 38.4kHz, FILT network = 1nF (22nF + 10k) fSYNC = 38.4kHz, FILT network = 1nF (22nF + 10k) 0.2V < (OUT - NICD) < 2V, 15mA_CHG = 1 0.2V < (OUT - NICD) < 2V, 1mA_CHG = 1 OUT = 2.8V, IOUT = 20mA, NICD = 3.3V Backup Mode, NICD = 3.3V 7 0.45 -3.5 5 210 270 268.8 15 1 25 25 1.5 3.5 10 325 kHz kHz kHz ms mA mA % Circuit of Figure 2, OUT = 3.0V, BATT = 1.1V Circuit of Figure 2, OUT = 3.0V, BATT = 1.0V Coast Mode, OUT = 1.8V to 4.9V Run Mode, OUT = 1.8V to 4.9V Coast or Run Mode, OUT = 1.8V to 4.9V IOUT = 1mA to 80mA, Run Mode BATT = 0.8V to 1.5V OUT = 3.0V IOUT = 80mA, COUT = 47F with ESR < 0.25 During the inductor charge cycle LX1 NMOS PMOS 76 480 80 15 -3.5 -3.5 30 100 25 25 83 70 600 0.45 0.65 720 0.9 1.3 115 40 3.5 3.5 170 mA mA % % mV mV mV % mVp-p mA 50 50 100 50 CONDITIONS MIN TYP MAX 70 70 70 UNITS ns ns ns ns ns ns ns
MAX847
3
_______________________________________________________________________________________
1-Cell, Step-Up Two-Way Pager System IC MAX847
ELECTRICAL CHARACTERISTICS (continued)
(OUT = 3.0V, BATT = 1.2V, NICD = 3.6V, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER LINEAR REGULATORS REG1 PMOS On-Resistance REG1 Supply Rejection (Note 15) REG1 Clamp Voltage REG2 Voltage Drop REG2 Load Regulation REG2 Supply Rejection (Note 15) REG3 Output Voltage REG3 Supply Rejection (Note 15) CONDITIONS OUT = 3.0V, IREG1 = 65mA f = 268.8kHz, CREG1 = 10F ceramic IOUT = 1mA, OUT = 4.9V TA = +25C TA = -40C to +85C IREG2 = 0 to 24mA, OUT = 3.0V, ROFS = 15k IREG2 = 0.1mA to 24mA f = 268.8kHz, CREG1 = 10F, ceramic, ROFS = 15k, COFS = 0.1F, IREG2 = 15mA IREG3 = 0 to 2mA f = 268.8kHz, CREG1 = 1F ceramic 30 0.96 40 0.58 7.5 -50 IOUT = 1mA Output = 5.5V 10mV overdrive 0.2 Measures NICD Measures BATT 1.2 0.2 10 Measures NICD Measures BATT At thresholds of 200mV, 800mV, and 1270mV At thresholds of 1200mV, 3200mV, and 5080mV At thresholds of 200mV, 800mV, and 1270mV -2.0 -15mV -3.0 -60mV -2.0 -15mV 1 4 2 8 40 10 2.0 +15mV 3.0 +60mV 2.0 +15mV 4 16 15 3.2 3.15 120 155 9 40 1.0 50 0.60 16 -3 30 1 15 0.63 30 50 400 250 50 1.27 5.08 1.27 1.04 MIN TYP 1.5 25 3.3 3.4 3.45 190 MAX 3.1 UNITS dB V mV mV dB V dB V mV nA mV nA s V V V mV mV mV % % % mV mV
DATA-ACQUISITION AND VOLTAGE MONITORS LBI/RSIN Input Threshold Falling input LBI/RSIN Input Hysteresis (Note 15) LBI/RSIN Input Current LBO/RSO Output Low LBO/RSO Output Leakage LBO/RSO Response Time (Note 15) CH0 Threshold Range (Note 15) CH1 Threshold Range (Note 15) CH2 Threshold Range (Note 15) CH0 Threshold Resolution (Note 15) CH1 Threshold Resolution (Note 15) CH2 Threshold Resolution (Note 15) CH0 Error CH1 Error CH2 Error CH0 Input Hysteresis (Note 15) CH1 Input Hysteresis (Note 15)
4
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1-Cell, Step-Up Two-Way Pager System IC
ELECTRICAL CHARACTERISTICS (continued)
(OUT = 3.0V, BATT = 1.2V, NICD = 3.6V, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER CH2 Input Hysteresis (Note 15) CH0 Input Current CH Comparator Response Time (Note 15) Note 1: Note 2: CH0 = 0.2V to 1.27V 10mV overdrive CONDITIONS MIN 1 -100 0.6 TYP 2 MAX 4 100 1.0 UNITS mV nA s
MAX847
Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9:
Note 10: Note 11: Note 12: Note 13: Note 14: Note 15:
Specifications to -40C are guaranteed by design, not production tested. This is not a tested parameter, since the IC is powered from OUT, not BATT. The only limitation in the BATT range is the inability to generate more than 5 times, or less than 1.15 times the BATT voltage at OUT. This is due to PWM controller duty-cycle limitations in Run Mode. Minimum start-up voltage is tested by determining when the LX pins can draw at least 50mA for 1s (min) at a 50kHz (min) repetition rate. This guarantees that the IC will deliver at least 200A at the OUT pin. This supply current is drawn from the OUT pin. Current drain from the battery depends on voltages at BATT and OUT and on the DC-to-DC converter's efficiency. Current into BATT pin in addition to the supply current at OUT. This current is roughly constant from Coast to Run Mode. Current into NICD pin when NICD isn't being charged and isn't regulating OUT. Current into NICD pin when NICD is regulating OUT. Doesn't include current drawn from OUT by the rest of the circuit. Measured by setting the OUT regulation point to 2.8V and holding OUT at 3.0V. Current into NICD pin when BATT and OUT are both at 0V. This test guarantees that NICD won't draw significant current when the main battery is removed and backup is not activated. Serial-interface timing specifications are not tested and are provided for design guidance only. Serial-interface functionality is tested by clocking data in at 5MHz with a 50% duty-cycle clock and checking for proper operation. With OUT set below 2.5V, the serial-interface clock frequency should be reduced to 1MHz to ensure proper operation. This specification is not directly tested but is guaranteed by correlation to LX on-resistance and current-limit tests. Measured by using the internal feedback network and Coast-Mode error comparator to regulate OUT. Doesn't include ripple voltage due to inductor currents. Measured by using the internal feedback network and Run-Mode error comparator to regulate OUT. Doesn't include ripple voltage due to inductor currents. Uses the OUT measurement techniques described for the OUT Error, Coast Mode, and OUT Error Run Mode specifications. PLL acquisition characteristics depend on the impedance at the FILT pin. The specification is not tested and is provided for design guidance only. The limits in this specification are not guaranteed and are provided for design guidance only.
__________________________________________Typical Operating Characteristics
(Circuit of Figure 2, TA = +25C, unless otherwise noted.)
EFFICIENCY vs. LOAD CURRENT (RUN MODE, VOUT = 3.0V)
MAX847TOC01
EFFICIENCY vs. LOAD CURRENT (COAST MODE, VOUT = 3.0V)
MAX847TOC02
EFFICIENCY vs. LOAD CURRENT (COAST MODE, VOUT = 2.4V)
VIN = 2.0V VIN = 1.5V
MAX847TOC03
100 90 EFFICIENCY (%) 80 70 60 50 40 1 10 100
100 90 EFFICIENCY (%) 80 70 VIN = 0.8V 60 50 40 VIN = 1.0V VIN = 2.0V VIN = 1.5V
100 90 EFFICIENCY (%) 80 70 VIN = 1.0V 60 50 40 VIN = 0.8V VIN = 1.2V
VIN = 0.8V VIN = 1.0V VIN = 1.2V VIN = 2.0V VIN = 1.5V
VIN = 1.2V
1000
0.1
1
10
100
1000
0.1
1
10
100
1000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
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5
1-Cell, Step-Up Two-Way Pager System IC MAX847
Typical Operating Characteristics (continued)
(Circuit of Figure 2, TA = +25C, unless otherwise noted.)
NO-LOAD BATTERY CURRENT vs. BATTERY VOLTAGE
MAX847-toc04
MAXIMUM LOAD CURRENT vs. BATTERY VOLTAGE
MAX847-TOC05
START-UP INPUT VOLTAGE vs. LOAD CURRENT
1.8 1.6 1.4 INPUT VOLTAGE (V) 1.2 1.0 0.8 0.6 0.4 0.2 VOUT = 3.0V COAST MODE 1 10 LOAD CURRENT (mA) 100
MAX847-TOC06
100
300 MAXIMUM LOAD CURRENT (mA) 250 200 150 100 50 0
2.0
(VOUT = 3.0V) RUN MODE
BATTERY CURRENT (mA)
80
60
40
COAST MODE
20 VOUT = 3.0V COAST MODE 0 0.5 1 1.5 2 BATTERY VOLTAGE (V)
0 0 0.5 1 1.5 2 2.5 BATTERY VOLTAGE (V)
NICD CHARGING CURRENT vs. NICD VOLTAGE
MAX847-TOC7
DR1 OR DR2 ON-RESISTANCE vs. VOUT
MAX847-toc08
25 NICD CHARGING CURRENT (mA)
3
20
2 RON () 1 5 15mA MODE VOUT = 4.9V 0 0 1 2 3 4 5 6 OUTPUT VOLTAGE (V) 0 0 1 2 3 4 5 VOUT VOLTAGE (V) 15
10
LX NOISE SPECTRUM (RUN MODE, SYNC OPERATION)
MAX847-09
REG2 NOISE SPECTRUM (RUN MODE)
MAX847TOC-10
20
100
0 NOISE (dBV) 100 200 300 400 500 600 NOISE (dBV)
80
-20
60
-40
40
-60
20
-80 FREQUENCY (kHz)
0 0.1 1 10 100 1000 10,000 FREQUENCY (kHz)
6
_______________________________________________________________________________________
1-Cell, Step-Up Two-Way Pager System IC
______________________________________________________________Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME LX1 SDI SDO PGND SCL LBO RSO REF CH0 RSIN LBI FILT SYNC OFS AGND DRGND DR1 DR2IN DR2 REG3 REG2 R2IN NICD REG1 OUT BATT CS RUN FUNCTION Connect LX1 to the inductor. LX1 is internally connected to an NFET that switches to PGND and a PFET that switches to OUT. Serial Data Input for SPI Interface Serial Data Output for SPI Interface Power Ground. Source of LX1 NFET. Serial Clock for SPI Interface Open-Drain Output for LBI Comparator Reset Output. Open drain goes low when RSIN drops below 0.6V. All serial registers are reset (or set) to POR state as well. 1.28V Reference. Bypass with a 1F capacitor. CH0 is compared to a 7-bit DAC that adjusts from 0.2V to 1.27V. The comparison result is sent to the CH0 OUT register. Reset Input. Triggers RSO and resets IC when input is below 0.6V. Comparator with hysteresis (18mV). Low-Battery Input. Triggers LBO and internal serial bit. An external RC network sets the PLL loop response (at SYNC) to adjust frequency lock time versus jitter: 1nF II (22nF + 10k). Connect to REF when SYNC is not used. Sync Input for PWM Switch Rate. A 38.4kHz input results in a 268.8kHz PWM rate (7 times the sync frequency). Resistor sets offset between OUT (or REG1 or any other point) and REG2. ROFS = 15k results in 150mV. Analog Ground Ground for DR1 and DR2 FET Sources Open-Drain FET Switch. Activated via the serial-interface bit. Logic Input. ANDed with the DR2ON bit to control the DR2 switch. Open-Drain FET. On via AND of the DR2ON bit and the DR2IN pin. 1V, 2mA Regulator Output. On via the serial interface. Low noise. 24mA REG2 Output. Linearly regulated to the voltage at the OFS pin (voltage difference = 10A * ROFS). REG2 isolates noise. REG2 Input. Connect to OUT, REG1, or another voltage source. 15mA or 1mA Settable Charge Current from OUT to 3-Cell NICD Stack. When the NICD_REG_ON bit is set (Table 2), NICD becomes an input to the linear regulator at OUT, and the DC-DC converter is off. PFET output connected to OUT. Output is clamped such that it cannot rise above 3.3V, regardless of the voltage set at OUT. DC-DC Converter Output and Feedback Point. Digitally controlled from 1.8V to 4.9V in 100mV steps (Table 6). Positive Connection to Battery. The IC is powered from OUT. Chip Select for SPI Serial Interface Run/Coast. Permits toggling between Run and Coast Modes via logic signal. Run is selected when either RUN or the internal RUN/COAST bit is high. Coast is selected when both are low.
MAX847
_______________________________________________________________________________________
7
1-Cell, Step-Up Two-Way Pager System IC MAX847
1-CELL BATTERY IN SCL 5 N LBO 6 - 0.6V CPLB + LBO CH0 9 FROM NICD S1 + CP0 - + CP1 - FROM BATTERY + CP2 - CH0 SERIAL I/O OV0-OV4 CH2 7 5 7-BIT CH DAC DAC0-DAC7 RESET CONTROL BACKUP REGULATOR CHARGE NICD OR BACKUP REGULATOR ROFS 15k 1mA/ 15mA CHARGE 23 NICD 5 3.3V CLAMP CLAMP ON WHEN OV4 = 1 25 - AR1 + P REG1 24 10F - AOUT + V FEEDBACK 1.28V REFERENCE CHG/REG 47F SDI 2 SDO 3 CS 27 RUN 28 26 BATT 22F L1 22H
MAX847
PWM (PFM IN COAST) RUN/ COAST x7 PLL P 12 CH1 13 1 N 4
LX1
LBI
11
PGND
FILT 1nF SYNC OUT 22nF 10k
REF 1F
8
14 22
OFS R2IN COFS 0.1F REG2
0.6V RSIN 10
+ CPRS -
10A 3.3V REG2 ON
- AR2 +
P 21
RSO
7 REG3 ON N 1.8 N N 1.8 1.0V - AR3 +
10F
P REG3 20 1.0V 1F
17 DR1
18 DR2IN
19 DR2
16 DRGND
15 AGND
Figure 1. Functional Diagram
8
_______________________________________________________________________________________
1-Cell, Step-Up Two-Way Pager System IC
______________ Detailed Description
The MAX847 contains several functional blocks that simplify the integration of power-supply and monitoring functions within a 1-cell powered system. They are described in the following subsections.
Voltage Regulators
Regulator outputs include the following: * OUT: Main switch-mode boost output * REG1: 1.5 switch and output voltage clamp. Switches REG1 to OUT and clamps REG1 at 3.3V when OUT is set to 3.4V or more. * REG2: Linear-regulated, 24mA low-noise output that regulates so that VOUT - VREG2 is a set difference voltage (10A * ROFS). Output peak-to-peak ripple is typically 2mV with a 10F bypass capacitor at REG2. REG2 clamps output at 3.3V. * REG3: Low-noise, 1V linear regulator that supplies 2mA.
AA ALKALINE
Main DC-DC Boost Converter (OUT) OUT is the main DC-DC converter's output. It supplies current from the internal synchronous-rectified boost regulator and needs no external FETs or voltage-setting resistors. The output voltage (V OUT) is adjusted from 1.8V to 4.9V in 100mV steps (Tables 2 and 6) by internal DAC control using a serial-data command. OUT can supply up to 80mA, less the current supplied to the other regulators (REG1, REG2, and REG3). OUT can also be put into a low-current, pulse-skipping Coast Mode (13A typical quiescent current) by resetting the RUN/COAST serial input bit and holding the RUN pin at 0V. OUT supplies up to 40mA in Coast Mode. Typically, when changing from Run to Coast Mode, a lower OUT voltage is also set (Table 5) to further reduce system operating current. The extent of this reduction depends on the minimum operating voltage of the system components when they are in standby or sleep states.
MAX847
C5 22F R1 330k REG1 R5 6 A/D IN SERIAL I/O 9 27 5 2 3 17 19 18 16 LBO CH0 CS SCL SDI SDO DR1 DR2 DR2IN DRGND R2 470k 26 BATT 11 LBI OUT PGND REG1 LX1 1 25 4 24
L1 22H
MBRO52OL C1 47F C6 0.1F CERAMIC 3.0V LOGIC
MAX847
R2IN OFS 22 14 C7 COFS 0.1F 21
C2 10F R6 ROFS 15k C3 10F 20 C4 1F 10 7 23 1V RCVR R6
REG2
2.85V ANALOG R3 1.3M R4 470k TO C RESET TO RF PA
1.8 DRIVERS
REG3
38.4kHz
13 12 R7 10k C9 22nF RUN 8 C8 0.1F COAST
SYNC FILT REF RUN 28 AGND 15
RSIN RSO NICD
C10 1nF
3-CELL NiCd
Figure 2. Standard Application Circuit
_______________________________________________________________________________________ 9
1-Cell, Step-Up Two-Way Pager System IC MAX847
OUT can be set as low as 1.8V; however, some run mode functions are limited when VOUT is below 2.5V: * The allowed serial-interface clock rate is reduced. * Internal LX FET and DR1 and DR2 on-resistance increases.
25 2N2907 Q1 12 7 R8 1M R6 1M C1
OUT
MAX847
FILT RSO
Logic Supply (REG1) REG1 is not a regulator in the conventional sense, but rather a 1.5 PFET that acts as either a switch or a voltage clamp, depending on the programmed OUT voltage. When OUT is set to 3.3V or less, REG1 operates as a switch. When OUT is set to 3.4V or more, the REG1 output clamps at 3.3V. This arrangement limits VREG1 to an acceptable voltage for logic when OUT is programmed to a higher voltage (typically >4V) for charging (see Charger Circuit and Backup Linear Regulator sections). Low-Noise Analog Supply (REG2) REG2 is a linear, 24mA low-dropout regulating circuit whose input is R2IN. The REG2 output (VREG2) is set by ROFS. ROFS does not set an absolute voltage, but rather an offset level from R2IN (Figure 2). VREG2 is set by:
VREG2 = VR2IN - 10A * ROFS Typically R2IN and R OFS are tied to OUT, in which case: VOUT - VREG2 = 10A * ROFS ROFS adjusts VOUT - VREG2 to allow REG2 noise rejection to be traded for voltage drop and consequent efficiency loss. A 15k (typical) ROFS value sets a 150mV voltage difference. R2IN typically is supplied from OUT or REG1 but can be connected elsewhere as long as the voltage applied to R2IN does not exceed VOUT. For lowest output noise on REG2, connect R2IN to REG1. Note that the REG2 output also clamps at 3.3V.
Figure 3. Add PNP to allow start-up in Run Mode before the SYNC input clock is active.
With no SYNC clock, and FILT tied to REF, the DC-DC converter nominally operates at 270kHz when in Run Mode. The Run Mode switching frequency has no relation to the serial-data clock rate. On initial power-up, the MAX847 is designed to start in Coast Mode, with Run Mode normally commanded by system via the serial interface, or the RUN pin, after the system has started. Under some circumstances, the MAX847 may power up in Run Mode. These circumstances are: 1) If a SYNC clock is not used (REF tied to FILT). 2) If the SYNC clock is used and is provided at initial power-up when REG1 is 1.5V or higher. 3) If the SYNC clock is used, the connection shown in Figure 3 is added, and the SYNC clock is present when RSO is cleared (logic high). These choices are outlined in Table 1.
Voltage Detectors (LBO and Reset)
The MAX847 contains two voltage-detector inputs: LBI and RSIN. The LBI and RSIN comparator outputs are open-drain pins (LBO and RSO) for a real-time hardware output. LBO is also readable via the serial interface. Both LBI and RSIN trigger at a 0.6V input threshold and have about 18mV hysteresis. RSO also triggers the MAX847 internal power-on reset (POR).
Low-Noise, 1V Analog Supply (REG3) REG3 is a 1V, low-noise linear regulator that supplies up to 2mA. REG3's input is internally connected to REG2.
PWM Frequency Synchronization
The MAX847 DC-DC converter operates with or without a clock at the SYNC input. If a SYNC clock is used, a PLL filter network must be connected at FILT (see R7, C9, and C10 in Figure 2). The DC-DC converter (in Run Mode) operates at 7f SYNC . The MAX847 is designed for a 38.4kHz SYNC clock and hence a 268.8kHz switching frequency. If a SYNC clock is not used then FILT must be tied to REF and R7, C9, and C10 should be omitted. Note that if a SYNC clock is not used, and FILT is not connected to REF, the MAX847 will not enter Run Mode.
10
7-Bit ADC (CH0 Input and CH1, CH2)
Three analog channels are compared to a 7-bit, serially programmed digital-to-analog converter (CH DAC). The CH DAC voltage can be varied in 10mV steps from 200mV to VREF - 1LSB (or 1.27V) (Table 2). CH0 is an external input, while CH1 and CH2 are signals internally generated from the NICD and BATT pins. NICD is internally divided by four before being compared to CH DAC, while BATT directly connects to CH2.
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1-Cell, Step-Up Two-Way Pager System IC MAX847
Table 1. Run and Coast Mode Start-Up Requirements
SYNC OPERATION CIRCUIT CONNECTION 1) Connect REF to FILT 2) Remove R7, C9, and C10 START-UP MODE CAPABILITY Can start in either Coast or Run Mode by tying RUN pin appropriately. In Run Mode the DC-DC converter operates at 270kHz. Can start in either Coast or Run Mode by tying RUN pin appropriately. In Run Mode the DC-DC converter operates at 7fSYNC once the SYNC clock is applied. Can start in either Coast or Run Mode by tying RUN pin appropriately. In Run Mode the DC-DC converter operates at 7fSYNC once the SYNC clock is applied.
No SYNC clock is used.
On initial power-up, system can supply SYNC clock to MAX847 when REG1 is greater than 1.5V. On initial power-up, system can supply SYNC clock to MAX847 before, or concurrent with, RSO going high. On start-up, system does not supply SYNC clock to MAX847 until after RSO goes high.
Use standard Figure 2 circuit
Add Q1 as shown in Figure 3
Use standard Figure 2 circuit
Must start in Coast Mode. Run Mode may then be started by the system after start-up.
The comparison threshold voltages for each channel are described in the following equations: VTH(CH0: pin 9) = D * 10mV VTH (CH1: NICD) = D * 40mV VTH(CH2: BATT) = D * 10mV where D is the decimal equivalent of the binary code DAC0-DAC6 (Table 2). DAC0 is the LSB. A DAC code of 1111111 equates to D = 127. When all zeros are programmed, the CH DAC and CH_ comparators turn off. CH0, CH1, and CH2 comparison results reside in the three MSB locations of the output serial data (Table 5). The CH_ OUT data is delayed by one read cycle. In other words, each CH_ OUT bit is the result of the comparison made against the CH DAC voltage programmed during the previous serial-write operation. An analog-to-digital (A/D) conversion can be performed on a channel by using the system software to step through a successive-approximation routine or, if the input is partially known, by setting the CH DAC to a voltage near the estimated point and checking successive CH_ OUT bits. A faster A/D shortcut can be used for battery measurements when the goal is a "go, no go" determination. For this type of test, the CH DAC can simply be set to the desired limit, and CH_ OUT supplies the result on the next serial-write operation. One instance in which this shortcut saves time is during a battery-impedance check. The unloaded battery voltage can first be measured, if time allows, using one of the techniques described in the previous paragraph. Then the magni-
tude of the loaded voltage drop can be quickly checked with a single comparison to see if it is within the desired limit. The A/D circuitry can be invoked in both Run and Coast Mode.
Open-Drain Drivers
Two open-drain drivers (DR1 and DR2) are activated via the serial interface. DR1 and DR2 are grounded 1.8 (typical) NFETs that can sink up to 120mA. The maximum sink current is limited by on-resistance and package dissipation to about 240mA total sink current for both switches. Note that DR1 and DR2 are designed to sink current only from the main battery (BATT) and cannot be pulled above BATT. DR2 is controlled by an external input (DR2IN) as well as a serial input bit. DR2IN is ANDed with the DR2ON serial-control bit, allowing DR2 to drive an audio beeper. The audio-frequency clock is applied to DR2IN, and ON/OFF gating is applied to DR2ON. Both DR2IN (pin 18) and DR2ON (serial bit) must be high for DR2 to switch on. DR1 is controlled only by DR1ON (serial bit).
Run and Coast Modes
The MAX847's default mode is Coast. Run Mode is selected by either serial command (Table 2) or by pulling the RUN pin high. The RUN serial bit and the RUN pin are logically ORed. Both must be low to implement Coast Mode. In Coast Mode, the DC-DC converter pulses only as needed to satisfy the load, holding MAX847 operating current to typically 13A. In Run Mode the DC-DC converter employs fixed-frequency
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1-Cell, Step-Up Two-Way Pager System IC MAX847
pulse width modulation (PWM), as well as synchronization, to minimize noise. Some MAX847 functions are confined to Run Mode while others remain active in both Run and Coast. These are outlined as follows. Various circuit functions can be disabled as follows: Functions that always remain on are: * Serial I/O * Reference (REF) * OUT * REG1 * LBI, RSIN (and LBO, RSO) Functions that can be programmed on or off are (Table 1): * DR1 and DR2 * REG2 and REG3 * NICD charger (Note: This may overload OUT if turned on in Coast Mode when other loads are present) * NICD backup regulator * CH0, CH1, CH2 and CH DAC Functions that always turn off in Coast Mode are: * SYNC and PLL circuits * DC-DC PWM control circuits
Power-On Reset
The MAX847 has an internal POR circuit (VOUT < 1.6V) to ensure an orderly power-up when a battery is first applied. This feature is separate from the RSO comparator; however, if RSO goes low during operation, all serial registers are set to the same predetermined states as on power-up. The POR states for each register are listed in Table 3. Note that the MAX847 always comes out of reset in Coast Mode; consequently, it cannot supply full power until Run Mode is selected by either the RUN pin or serial command. System software cannot exercise full load current until Run Mode is enabled.
Charger Circuit
A charger current source from OUT to NICD is activated via a serial bit (Table 2). The current source can charge a small 3-cell NICD or NIMH battery (typically coin cell) or a 1-cell lithium battery. The charge current can be set to either 15mA or 1mA. When both 15mA and 1mA are set, the charger runs at 15mA. OUT sets the maximum charge (or float) voltage. When charging is implemented, VOUT must also be set high enough to allow sufficient headroom for the charger current source. The VOUT - VNICD difference should normally be between 0.2V and 0.5V. Charger current vs. output voltage is graphed in the Typical Operating Characteristics. Note also that charging current reduces the OUT current available for other loads.
Table 2. Serial-Bit Assignments
R2 (MSB) 0 0 0 0 1 R1 0 0 1 1 DAC6 R0 0 1 0 1 DAC5 D4 DR2_ON X OV4 X DAC4 D3 DR1_ON LBO_Sets_ BACKUP OV3 X DAC3 D2 REG3_ON BACKUP OV2 X DAC2 D1 REG2_ON 15mA_CHG OV1 X DAC1 D0 RUN/ COAST 1mA_CHG OV0 X DAC0
Table 3. Serial-Bit Power-On-Reset (POR) States
R2 0 0 0 0 1 12 R1 0 0 1 1 POR = 0 R0 0 1 0 1 POR = 0 D4 POR = 0 X POR = 0 X POR = 0 D3 POR = 0 POR = 0 POR = 1 X POR = 0 D2 POR = 0 POR = 0 POR = 1 X POR = 0 D1 POR = 0 POR = 0 POR = 0 X POR = 0 D0 POR = 0 POR = 0 POR = 0 X POR = 0
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1-Cell, Step-Up Two-Way Pager System IC
Backup Linear Regulator
The BACKUP serial input bit turns on the backup regulator, which sources current from NICD to OUT. This regulator backs up OUT by using the rechargeable battery (at NICD) when the main battery (at BATT) is depleted or removed. The backup regulator pass device's resistance is typically 5, so it can typically supply 20mA with only 100mV of dropout. All DC-DC converter and charging circuitry is disabled when the backup regulator is turned on, but all other functions remain active. Activate BACKUP manually by serial command, or set it to trigger automatically when LBO goes low. coming out of reset, the P (still reset by RSO) would not be able to provide the device with serial instructions to turn on.
MAX847
Serial Interface
The MAX847 has an SPI-compatible serial interface. The serial-interface lines are Chip Select (CS), Serial Clock (SCL), Serial Data In (SDI), and Serial Data Out (SDO). Serial input data is arranged in 8-bit bytes. Most bytes contain a 3-bit address pointer (R2, R1, R0) along with 5 bits of input data (D4-D0). For common operations such as selecting Run or Coast Mode, activating REG2 or REG3, or turning on DR1 or DR2, only the 000 (R2, R1, R0) address register needs to be written. The serial input data format for all MAX847 operations is outlined in Tables 2, 3, and 4.
Automatic Backup
Setting the LBO_Sets_BACKUP serial bit (Table 2) programs the IC so that when LBO goes low, the backup regulator automatically turns on without instructions from the microprocessor (P). When the LBO_ Sets_BACKUP bit is 0, the backup regulator is turned on only by setting the BACKUP bit. The BACKUP bit also overrides the LBO_Sets_BACKUP bit. Figure 4 shows the logic for this function. If the main battery is depleted, and the NICD battery is drained during backup, RSO goes low while the backup regulator is supplying OUT (if RSI is used to monitor OUT or REG1). When RSO falls, the serial registers reset to their POR states (with the DC-DC converter on in Coast Mode and the backup regulator off, Tables 2, 3, and 4). This prevents the IC from getting hung up with the DC-DC converter off when a new main battery is inserted. This sequence is required because if the MAX847 did not default to "DC-DC converter on" when
15mA_CHG TO CHARGER CONTROL
1mA_CHG
LBO LBO_SETS_BACKUP
TO BACKUP REGULATOR BACKUP
Figure 4. Logic for Charger Control and BACKUP, and for LBO_Sets_BACKUP Serial Input Bits
Table 4. Input-Bit Function Description
INPUT BIT RUN/COAST REG2_ON, REG3_ON DR1, DR2 1mA_CHG, 15mA_CHG FUNCTION 1 = Run Mode, 0 = Coast Mode (POR state is Coast Mode). 1 = Turn on selected regulator (POR state is off). 1 = Turn on selected switch (POR state is off). 1 = Turn on selected charge current to NICD. If both are set, the charge current is 15mA (POR state is off). 1 = Turn on backup linear regulator from NICD to OUT and disable DC-DC converter (POR state is BACKUP off). Setting this bit overrides 1mA_CHG, 15mA_CHG, and LBO_Sets_BACKUP (Figure 1). 1 = Allow LBO to turn on backup regulator and disable DC-DC converter (POR state is no connection between LBO and BACKUP). Sets OUT Output Voltage (POR state is VOUT = 3.0V). Sets 7-bit CH DAC voltage for A/D conversion (POR state is all zeros with DAC and comparators off). ______________________________________________________________________________________ 13
BACKUP
LBO_Sets_BACKUP OV0-OV4 DAC0-DAC6
1-Cell, Step-Up Two-Way Pager System IC MAX847
CS ***
tCSH SCLK
tCSS
tCL
tCH
tCSH
*** tDS tDH
DIN tDV DOUT
*** tDO *** tTR
Figure 5. Detailed Serial-Interface Timing
CS
SCL
SDO
D7
D6
D5
D4
0
0
0
0
SDI
R2
R1
R0
D4
D3
D2
D1
D0
Figure 6. CS, SCL, SDO, and SDI Serial Timing
Serial data is clocked in and out MSB first. Input data is latched on the CLK rising edge, and output data is shifted out on the CLK falling edge. When CS goes low, DO immediately contains the MSB output bit (D7). D6 is not clocked out until the falling clock edge that follows the first rising clock edge after a Chip Select. See the timing diagrams in Figures 5 and 6.
SPI writes and reads concurrently, so it may be necessary to perform dummy writes in order to read output data. Four output data bits (D7-D4, Table 5) are sent from SDO each time a serial operation occurs. When R2 = 0, R0 and R1 are address pointers. However, when R2 = 1, the 7 remaining bits (R1, R0 and D4-D0) become DAC programming bits. This vio-
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1-Cell, Step-Up Two-Way Pager System IC MAX847
Table 5. Serial Output Data
D7 (MSB) D6 D5 D4 D3-D0 FUNCTION CH_ OUT and LBO output bits. A 1 indicates that the selected channel (CH_) voltage is greater than the CH DAC voltage or that LBI is less than 0.6V.
CH2_OUT
CH1_OUT
CH0_OUT
LBO
X
Table 6. VOUT Output Voltage
SERIAL-DATA BIT OV4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 OV3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 OV2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 OV1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 OV0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 VOUT (V)
lation of programming etiquette (R1 and R0 are sometimes address bits and other times data bits) allows the CH DAC to be loaded with only one write operation. Writing all zeros to the CH DAC turns it, the CH0, CH1, and CH2 comparators, and the NICD and BATT voltagesensing resistors off to minimize current consumption. This reduces current drain from OUT by about 30A.
Applications Information
Component Selection
The MAX847 requires minimal design calculation and is optimized for the component values shown in Figure 2. However, some flexibility in component selection is still allowed, as described in the following text. A list of suitable components is provided in Table 7. Inductor L1 is nominally 22H, but values from 10H to 47H should be satisfactory. The inductor current rating should be 500mA or more if full output current (80mA) is needed. If less output current is required, the inductor current rating can be reduced proportionally but should never be less than 250mA. Inductor resistance should be minimized for best efficiency, but since the MAX847 N-channel switch resistance is typically 0.45, efficiency does not improve significantly for coil resistances below 0.2. Filter capacitors C1-C4 should be low-ESR types (tantalum or ceramic) for lowest ripple and best noise rejection. A high-frequency 0.1F ceramic cap should be used in parallel to reduce transient noise at OUT. The values shown in Figure 2 are optimized for each output's rated current. Lower required output current allows smaller capacitance values. Resistors at the LBI and RSIN inputs set the voltage at which the LBO and RSO outputs trigger. The voltage threshold for both LBI and RSI is 0.6V. The resistors required to set a desired trip voltage, VTRIP (Figure 2), are calculated by: R1 = R2[(VTRIP(LBO) / 0.6) - 1] R3 = R4[(VTRIP(RSO) / 0.6) - 1]
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1-Cell, Step-Up Two-Way Pager System IC MAX847
Table 7. External Components
SUPPLIER INDUCTORS (22H) Coilcraft DT1608C-223 LQH4N220K Murata LQH3C221 CD54-220 Sumida CD43-220 CDRH62B-220 TDK CAPACITORS AVX Marcon Sprague NLC565050-220K TPS series THCR series 595D series 0.16, 3.18mm high, shielded 0.94, 2.6mm high, low current, low cost 0.71, 2mm high, low current, low cost 0.18, 4.5mm high 0.378, 3.2mm high 0.34, 3mm high, shielded 0.43, 5mm high Tantalum Ceramic Tantalum PART NO. COMMENTS
Board Layout and Noise Reduction
The MAX847 makes every effort in its internal design to minimize noise and EMI. Nevertheless, prudent layout practices are still suggested for best performance. Recommendations include: 1) Keep trace lengths at L1 and LX1, as well as at PGND, as short and as wide as possible. Since LX1 swing between VBAT and VOUT at a high rate, minimizing LX1 trace length serves to reduce the PC board area that can act as an antenna. 2) The filter capacitors at OUT, REG1, REG2, and REG3 should be placed as close as possible to their respective pins (no more than 0.5mm away). 3) A shielded inductor at L1 will minimize radiation noise, but may not be essential. Toroids will also exhibit EMI performance similar to that of shielded coils. 4) The LX1, OUT, and PGND pins are located at the uppermost part of the IC to facilitate PC layout. Keep power components in this area to minimize coupling to other parts of the circuit. Other pins in this area are digital and are not affected by close proximity to switching nodes. 5) Use a separate short wide ground trace for PGND and the ground side of the BATT and OUT filter capacitors. Tie this trace to the ground plane.
Sprague 595D series STORAGE CAPACITOR (optional at Tantalum NICD pin) Polystor A-10300 1.5F
To minimize battery drain, use large values for R2 and R4 (>100k) in the above equations; 470k is a good starting value. See the Low-Noise Analog Supply (REG2) section for information on selecting ROFS. Since LBO and RSO are open-drain outputs, pull-up resistors (R5, R6) are usually required. Normally these will be pulled up to REG1. 100k is recommended as a compromise between response time and current drain, although other values can be used. Since LBI and RSO are high (open circuit) during normal operation, current normally does not flow in R5 and R6 until a low-battery or reset event occurs.
Pin Configuration
TOP VIEW
LX1 1 SDI 2 SDO 3 PGND 4 SCL 5 LBO 6 RSO 7 REF 8 CH0 9 RSIN 10 LBI 11 FILT 12 SYNC 13 OFS 14 28 RUN 27 CS 26 BATT 25 OUT 24 REG1
MAX847
23 NICD 22 R2IN 21 REG2 20 REG3 19 DR2 18 DR2IN 17 DR1 16 DRGND 15 AGND
Logic Levels
Note that since the MAX847's internal logic is powered from REG1, the input logic levels at the digital inputs: DR2IN, RUN, SYNC, CS, SCL, and SDI, as well as the logic output levels of SDO, are governed by the voltage of REG1. Logic high inputs at these pins should not exceed VREG1. Digital inputs should either be driven from external logic (or a P) powered from REG1, or by open-drain logic devices that are pulled up to REG1.
QSOP
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1-Cell, Step-Up Two-Way Pager System IC
Package Information
QSOP.EPS
MAX847
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1-Cell, Step-Up Two-Way Pager System IC MAX847
NOTES
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